Home Research Team Publications CV Lattes Google Scholar ORCID

Papers in Periodics

  1. de Souza, Michelly; Doria, Rodrigo; Trevisoli, Renan; Barraud, Sylvain; Pavanello, Marcelo Antonio; "On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks", IEEE Transactions on Nanotechnology, v. 20, p. 234-242, 2021. DOI: 10.1109/TNANO.2021.3058885

  2. Trevisoli, R.; Pavanello, M. A.; Capovilla, C. E.; Barraud, S.; Doria, R.T.; "Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors", IEEE Transactions on Electron devices, v. 67, p. 2536-2543, 2020. DOI: 10.1109/ted.2020.2986141

  3. Costa, F. J.; Trevisoli, R.; Doria, R. T.; "Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors", Journal of Integrated Circuits and Systems, v. 15, p. 1-6, 2020. DOI: 10.29292/jics.v15i1.118

  4. Costa, F. J.; Trevisoli, R.; Doria, R. T.; "UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level", Journal of Integrated Circuits and Systems, v. 15, p. 1-5, 2020. DOI: 10.29292/jics.v15i2.194

  5. Graziano Junior, N.; Trevisoli, R.; Doria, R. T.; "Analysis of the Correlation Between NBTI Effect and the Surface Potential in Junctionless Nanowire Transistors", Journal of Integrated Circuits and Systems, v. 15, p. 1-5, 2020. DOI: 10.29292/jics.v15i2.196

  6. Picoli Junior, M. P.; Trevisoli, R.; Doria, R.T.; "Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires", Journal of Integrated Circuits and Systems, v. 15, p. 1-5, 2020. DOI: 10.29292/jics.v15i2.200

  7. Pavanello, M. A.; Cerdeira, A.; Doria, R. T.; Ribeiro, T. A.; Herrera, F. A.; Estrada, M.; "Compact Modeling of Triple Gate Junctionless Mosfets for Accurate Circuit design in a Wide Temperature Range", Solid-State Electronics, v. 159, p. 116-122, 2019. DOI: 10.1016/j.sse.2019.03.034

  8. Trevisoli, Renan; Doria, Rodrigo T.; de Souza, Michelly; Barraud, Sylvain; Pavanello, Marcelo A.; "Junctionless Nanowire Transistors Parameters Extraction Based on Drain Current Measurements", Solid-State Electronics, v. 158, p. 37-45, 2019. DOI: 10.1016/j.sse.2019.05.004

  9. Trevisoli, Renan; Doria, Rodrigo Trevisoli; Barraud, Sylvain; Pavanello, Marcelo Antonio; "Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors", Microelectronic Engineering, v. 215, p. 111005, 2019. DOI: 10.1016/j.mee.2019.111005

  10. Pavanello, M. A.; Trevisoli, R.; Doria, R.T.; de Souza, M.; "Static and dynamic compact analytical model for junctionless nanowire transistors", Journal of Physics-Condensed Matter, v. 30, p. 334002, 2018. DOI: 10.1088/1361-648x/aad34f

  11. Doria, Rodrigo Trevisoli; Trevisoli, Renan; de Souza, Michelly; Pavanello, Marcelo Antonio; "Physical Insights on the Dynamic Response of SOI n- and p-Type Junctionless Nanowire Transistors", Journal of Integrated Circuits and Systems, v. 13, p. 1-7, 2018. DOI: 10.29292/jics.v13i1.17

  12. Doria, R. T.; Trevisoli, R.; de Souza, M.; Barraud, S.; Vinet, M.; Faynot, O.; Pavanello, M. A.; "Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization", Microelectronic Engineering, v. 178, p. 17-20, 2017. DOI: 10.1016/j.mee.2017.04.014

  13. Trevisoli, R.; Doria, R. T.; de Souza, M.; Barraud, S.; Vinet, M.; Casse, M.; Reimbold, G.; Faynot, O.; Ghibaudo, G.; Pavanello, M. A.; "A New Method for Series Resistance Extraction of Nanometer MOSFETs", IEEE Transactions on Electron Devices, v. 64, p. 2797-2803, 2017. DOI: 10.1109/ted.2017.2704928

  14. Doria, R.T.; Flandre, D.; Trevisoli, R.; de Souza, M.; Pavanello, M. A.; "Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures", Semiconductor Science and Technology, v. 32, p. 095005, 2017. DOI: 10.1088/1361-6641/aa7659

  15. Assalti, R.; Doria, R.T.; Flandre, D.; de Souza, M.; "Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully depleted SOI nMOSFETs", Journal of Integrated Circuits and Systems, v. 12, p. 62-70, 2017. DOI: 10.29292/jics.v12i2.452

  16. Paz, B. C.; Doria, R. T.; Casse, M.; Barraud, S.; Reimbold, G.; Vinet, M.; Faynot, O.; Pavanello, M. A.; "Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K", Microelectronics Reliability, v. 79, p. 111-118, 2017. DOI: 10.1016/j.microrel.2017.10.008

  17. Trevisoli, R.; de Souza, M.; Doria, R. T.; Kilchtyska, Valeriya; Flandre, D.; Pavanello, M. A.; "Junctionless nanowire transistors operation at temperatures down to 4.2 K", Semiconductor Science and Technology, v. 31, p. 114001, 2016. DOI: 10.1088/0268-1242/31/11/114001

  18. Trevisoli, Renan D.; Doria, R. T.; de Souza, Michelly; Barraud, Sylvain; Vinet, Maud; Pavanello, Marcelo Antonio; "Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors", IEEE Transactions on Electron devices, v. 63, p. 856-863, 2016. DOI: 10.1109/TED.2015.2507571 DOI: 10.1088/0268-1242/31/11/114001

  19. de Souza, Michelly; Flandre, Denis; Doria, R. T.; Trevisoli, Renan D.; Pavanello, Marcelo Antonio; "On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration", Solid-State Electronics, v. 117, p. 152-160, 2016. DOI: 10.1016/j.sse.2015.11.018

  20. Trevisoli, Renan; Doria, Rodrigo Trevisoli; de Souza, Michelly; Pavanello, Marcelo Antonio; "Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors", Microelectronic Engineering, v. 147, p. 23-26, 2015. DOI: 10.1016/j.mee.2015.04.040

  21. Doria, Rodrigo Trevisoli; de Souza, Márcio Alves Sodré; Martino, João Antonio; Simoen, Eddy; Claeys, Cor; Pavanello, Marcelo Antonio; "In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs", Microelectronic Engineering, v. 147, p. 92-95, 2015. DOI: 10.1016/j.mee.2015.04.056

  22. Trevisoli, R.; Doria, R. T.; de Souza, M.; Pavanello, M. A.; "Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors", IEEE Transactions on Electron devices, v. 61, p. 1575-1582, 2014. DOI: 10.1109/TED.2014.2309334

  23. Novo, C.; Giacomini, R. C.; Doria, R. T.; Afzalian, A.; Flandre, D.; "Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures", Semiconductor Science and Technology (Print), v. 29, p. 075008, 2014. DOI: 10.1088/0268-1242/29/7/075008

  24. Doria, R. T.; Trevisoli, R.; de Souza, M.; Pavanello, M. A.; "Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors", Solid-State Electronics, v. 96, p. 22-26, 2014. DOI: 10.1016/j.sse.2014.04.019

  25. Doria, R. T.; Trevisoli, R.; de Souza, M.; Estrada, M.; Cerdeira, A.; Pavanello, M. A.; "The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime", Journal of Integrated Circuits and Systems, v. 9, p. 110-117, 2014. DOI: 10.29292/jics.v9i2.396

  26. Trevisoli, R D; Doria, R. T.; de Souza, M.; Pavanello, M. A.; "A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors", Solid-State Electronics, v. 90, p. 12-17, 2013. DOI: 10.1016/j.sse.2013.02.059

  27. Doria, R. T.; Trevisoli, R D; de Souza, M.; Pavanello, M. A.; "Trap density characterization through low-frequency noise in junctionless transistors", Microelectronic Engineering, v. 109, p. 79-82, 2013. DOI: 10.1016/j.mee.2013.03.090

  28. Cerdeira, A.; Estrada, M.; Iniguez, B.; Trevisoli, R D; Doria, R. T.; de Souza, M.; Pavanello, M. A.; "Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors", Solid-State Electronics, v. 85, p. 59-63, 2013. DOI: 10.1016/j.sse.2013.03.008

  29. Trevisoli, R D; Doria, R. T.; de Souza, M.; Pavanello, M. A.; "Analysis of the leakage current in junctionless nanowire transistors", Applied Physics Letters, v. 103, p. 202103, 2013. DOI: 10.1063/1.4829465

  30. Doria, R. T.; Martino, J. A.; Simoen, Eddy; Claeys, Cor; Pavanello, Marcelo Antonio; "Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates", Solid-State Electronics, v. 90, p. 121-126, 2013. DOI: 10.1016/j.sse.2013.02.042

  31. Trevisoli, Renan D.; Doria, R. T.; de Souza, Michelly; Pavanello, Marcelo Antonio; "Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors", Journal of Integrated Circuits and Systems, v. 8, p. 116-124, 2013. DOI: 10.29292/jics.v8i2.382

  32. Doria, R. T.; Trevisoli, R D; de Souza, M.; Pavanello, M. A.; "Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature", Journal of Integrated Circuits and Systems, v. 7, p. 121-129, 2012. DOI: 10.29292/jics.v7i2.364

  33. Trevisoli, R D; Doria, R. T.; de Souza, M.; Das, S; Ferain, I.; Pavanello, M. A.; "The zero temperature coefficcient in junctionless nanowire transistors", Applied Physics Letters, v. 101, p. 1, 2012. DOI: 10.1063/1.4744965

  34. Trevisoli, R D; Doria, R. T.; De Souza, M.; Das, S; Ferain, I.; Pavanello, M. A.; "Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors", IEEE Transactions on Electron devices, v. 59, p. 3510-3518, 2012. DOI: 10.1109/TED.2012.2219055

  35. Doria, R. T.; Simoen, E.; Claeys, C.; Martino, J. A.; Pavanello, M. A.; "Harmonic Distortion of 2-MOS Structures for MOSFET-C Filters Implemented with n-Type Unstrained and Strained FinFETs", Solid-State Electronics, v. 62, p. 99-105, 2011. DOI: 10.1016/j.sse.2011.01.045

  36. Doria, R. T.; Pavanello, M. A.; Trevisoli, R D; Souza, M.; Lee, C. W.; Ferain, I.; Dehdashti-Akhavan, N.; Yan, R.; Razavi, P.; Yu, R.; Kranti, A.; Colinge, J. P.; "Analog Operation Temperature dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion", Journal of Integrated Circuits and Systems, v. 6, p. 114-121, 2011. DOI: 10.29292/jics.v6i2.347

  37. Doria, R. T.; Pavanello, M. A.; Trevisoli, R D; De Souza, M.; Lee, C. W.; Ferain, I.; Dehdashti-Akhavan, N.; Yan, R.; Razavi, P.; Yu, R.; Kranti, A.; Colinge, J. P.; "Junctionless Multiple-Gate Transistors for Analog Applications", IEEE Transactions on Electron Devices, v. 58, p. 2511-2519, 2011. DOI: 10.1109/TED.2011.2157826

  38. Trevisoli, Renan Doria; Doria, Rodrigo Trevisoli; de Souza, Michelly; Pavanello, Marcelo Antonio; "Threshold voltage in junctionless nanowire transistors", Semiconductor Science and Technology, v. 26, p. 105009, 2011. DOI: 10.1088/0268-1242/26/10/105009

  39. Souza, M.; Pavanello, M. A.; Trevisoli, R D; Doria, R. T.; Colinge, J. P.; "Cryogenic Operation of Junctionless Nanowire Transistor", IEEE Electron device Letters, v. 32, p. 1322-1324, 2011. DOI: 10.1109/LED.2011.2161748

  40. Doria, R. T.; Colinge, Jean-Pierre; Lee, Chi-Woo; Ferain, Isabelle; Akhavan, Nima dehdashti; Yan, Ran; Razavi, Pedram; Yu, Ran; Nazarov, Alexei N.; "Reduced electric field in junctionless transistors", Applied Physics Letters, v. 96, p. 073510, 2010. DOI: 10.1063/1.3299014

  41. Lee, Chi-Woo; Nazarov, Alexei N.; Ferain, Isabelle; Akhavan, Nima dehdashti; Yan, Ran; Razavi, Pedram; Yu, Ran; Doria, Rodrigo T.; Colinge, Jean-Pierre; "Low subthreshold slope in junctionless multigate transistors", Applied Physics Letters, v. 96, p. 102106, 2010. DOI: 10.1063/1.3358131

  42. Doria, R. T.; Cerdeira, A.; Martino, J. A.; Simoen, E.; Claeys, C.; Pavanello, M. A.; "Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation", IEEE Transactions on Electron Devices, v. 57, p. 3303-3311, 2010. DOI: 10.1109/TED.2010.2079936

  43. Doria, R. T.; Cerdeira, A.; Raskin, J. P.; Flandre, D.; Pavanello, M. A.; "Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation", Microelectronics, v. 39, p. 1663-1670, 2008. DOI: 10.1016/j.mejo.2008.02.006